iCatch V50M 双核 ARM 800MHz 芯鼎 凌阳科技 Sunplus 4K摄像机方案 SOC
二维码
SOC/DSP/IC/CPU型号 iCatch V50M
CPU架构 双核ARM cortex-A7处理器,最高800MHz
运行内存 System in package 4Gb LPDDR3 SDRAM
图像sensor接口 MIPI,LVDS
图像引擎ISP iCatch 自研ISP引擎
视频编码 H265/H.264/MJPEG
显示屏接口 BT.601/656/1120 digital interface
音频接口 支持内置模拟麦输入和I2S的外围音频IC
储存接口 SD/SDHC/SDXC, MMC, and eMMC4.5/5.0 interfaces
USB接口 USB 2.0 device and host
HDMI接口 内置HDMI接口
封装尺寸 V50M 433-ball HSBGA package with 15 mm x 15 mm x 1.6 mm
微信扫一扫咨询
产品参数
SOC/DSP/IC/CPU型号
iCatch V50M
CPU架构
双核ARM cortex-A7处理器,最高800MHz
运行内存
System in package 4Gb LPDDR3 SDRAM
图像sensor接口
MIPI,LVDS
图像引擎ISP
iCatch 自研ISP引擎
视频编码
H265/H.264/MJPEG
显示屏接口
BT.601/656/1120 digital interface
音频接口
支持内置模拟麦输入和I2S的外围音频IC
储存接口
SD/SDHC/SDXC, MMC, and eMMC4.5/5.0 interfaces
USB接口
USB 2.0 device and host
HDMI接口
内置HDMI接口
封装尺寸
V50M 433-ball HSBGA package with 15 mm x 15 mm x 1.6 mm
我知道了
产品详情

V50M 02 台湾芯鼎科技 iCatch.jpg


V50M

UHD 4K Camera Processor


The iCatch V50M is a system-on-chip solution that enables various high-end camera applications, such as DSC, action

camera, automotive camera, surveillance camera and more. Not only does it include a dual-core Rise CPU and

an OpenVG GPU, but it also integrates iCatch’s 6th generation image signal processor, H.265/H.264 Codec for

4K2K resolution, and a programmable imagine and computer vision DSP. Furthermore, a rich set of acceleration

engines are also incorporated into V50M to support the most advanced image processing technology, such as

multi-axis EIS, multi-frame super resolution and HDR.

V50M has 12 data lanes which supports a variety of sensor interfaces and raw image data capture at 1200M pixels/s and the image

signal processor works seamlessly with the JPEG engine and storage media controller to enable high-speed burst capture up to 300M

pixels/s. Audio codec, MIPI D-PHY and HDMI PHY are also included in V50M to minimize system BOM cost and to maximize design

flexibility. For connectivity, V50M comes with USB host and stand-alone SDIO interface for WiFi and 4G/LTE modem as well as

Ethernet MAC for Gigabit Ethernet.


FEATURES

Image Sensor Interface

 12-lane SubLVDS, HiSPI and MIPI-CSI2 serial interfaces

 Quad sensor inputs

 CMOS sensors up to 42M pixels resolution


Advanced Still Image Processing

 Raw data capture speed up to 1200M pixels/sec

 JPEG codec speed up to 300M pixels/sec

 Motion compensated temporal filtering for video noise reduction

 Real-time multi-frame HDR video

 Real-time super resolution enhancement for image zoom

 Real-time multi-axis electronic image stabilization (EIS)

 Real-time multi-segment rolling shutier correction (RSC)

 Advanced raw noise and high-ISO noise reduction technology

 Lens distortion correction (LDC) and dewarping engine

 Local tone mapping WDR video

 Edge enhancement over-shoot control

 Motion-based object tracking engine

 Face beautification

 Dual-core face detection and tracking engine

 Red-eye removal, blink detection, and smile detection


Video

 H.264 BP/MP/HP and H.265 MP up to Level 5

 Real-time encode and decode at 4K2Kp30

 H.264 CABAC/CAVLC and H.265 CABAC entropy coding

 Up to 8 simultaneous encoding streams

 Support I/P/B slice

 Advanced bitrate control

 Motion-JPEG up to 4K2K resolution


Memory

 32-bits DRAM controller up to 800MHz

 System in package 4Gb LPDDR3 SDRAM


Processor Cores

 Dual-Core ARM Cortex-A7 processors up to 800MHz

 iCatch image processing pipeline and acceleration engines

 Video DSP up to 400MHz which automatically offload Computer Vision tasks from CPU


Audio

 MPEG-1 layer 1/2, MP3, AAC, G.726

 Wind sound reduction filter and notch filter

 Dynamic range control

 I2S interface to external audio codec

 16-bit stereo audio ADC with microphone input

 16-bits mono audio DAC with 1 lineout to TV and 1 speaker output


Display Capability

 OpenVG and EGL graphic accelerator

 Real-timer vector graphic with sustainable performance at 1080p

 MIPI-DSI support

 On-chip HDMI controller and PHY

 BT.601/656/1120 digital interface

 On-chip PAL/NTSC encoder and TV DAC

 Dual display capacity (LCD and TV)


Peripherals

 NAND and SPI flash memory

 SD/SDHC/SDXC, MMC, and eMMC4.5/5.0

 USB 2.0 device and host controller with PHY

 Ethernet MAC with MII/RMII/GMII interface

 Many GPIO, PWM, UART, SPI, and I2C ports

 Real-time clock and watchdog timer

 Multiple channels of 12-bits SAR ADC

 Touch panel interface

 Stand-alone SDIO controller for wireless device


Package

 433-ball HSBGA package with 15 mm x 15 mm x 1.6 mm

 Operation temperature: 0°C to +70°C


v50 block diagram.jpg